Analogue, Mixed-Signal and RF Subsystem Design
Tetrivis provides design services of virtually any analogue and mixed-signal subsystem from DC to 15GHz in Bipolar, BiCMOS and CMOS process technologies ranging from 0.5um to 40nm nodes
Tetrivis is an agile company with various design models to suit all customer needs viz:
- Full-custom Schematic design into client repository (VPN access required)
- Full-custom Schematic and Layout design using Tetrivis tools (Netlist and GDSII deliverables)
- A combination of the above
Recent analogue, mixed-signal and RF subsystems designed by Tetrivis for various clients include:
- Ku-Band single-beam dual-polarisation Phased Array Transmit ASIC in 180nm SiGe BiCMOS
- Ku-Band single-beam dual-polarisation Phased Array Receive ASIC in 180nm SiGe BiCMOS
- Ku-Band dual-beam dual-polarisation Phased Array Transmit ASIC in 180nm SiGe BiCMOS
- Ku-Band dual-beam dual-polarisation Phased Array Receive ASIC in 130nm SiGe BiCMOS
- 1.7dB Noise Figure, 26dB gain, 0dBm IIP3, 1.2V, 1.8GHz-to-2.7GHz LNA for LTE-M in 65nm CMOS
- 70dB SNR, 1.1V, 70MHz-to-340MHz-clock-rate continuous-time Sigma-Delta ADC for FM/DAB in 40nm CMOS
- Extremely linear 1.2V Baseband-Filter + Complex IQ Modulator for LTE Transmit chain with 0.7GHz-to-3.8GHz frequency coverage in 65nm CMOS
- 1.4dB Noise Figure, 22dB gain, -6dBm IIP3, 1.2V, 0.7GHz-to-0.96GHz LNA for LTE Receive chain in 65nm CMOS
- 60dB SNR, 1.8V, 20MHz-to-130MHz-clock-rate switched-capacitor Sigma-Delta ADC for FM/DAB/DVB-T/DVB-T2/ISDB-T/ATSC in 180nm CMOS
- 2dB Noise Figure, 40dB gain, 1.5V, 40MHz-to-900MHz RF Front-End with 45dB gain control range, -20dBm to +17dBm IIP3 and +50dBm IIP2 for FM/DAB/DVB-T/DVB-T2/ISDB-T/ATSC in 130nm CMOS